`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/21 10:08:39
// Design Name: 
// Module Name: mealy_top_sim
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module moore_top_sim();
    reg clk_i = 1'b0;
    reg rst_i = 1'b0;
    reg set_i = 1'b0;
    reg [7:0] data_i = 1'b0;
    wire detect_o;
    
    mealy_top UUT(.rst_i(rst_i), .clk_i(clk_i), .set_i(set_i), .data_i(data_i), .detect_o(detect_o));
    
    always #1 begin clk_i = ~clk_i; end
    
    initial begin
        data_i = 8'b1001_0111; set_i = 'b1;
        #14 set_i = 0;
        #205 rst_i = 'b1;
        #10 rst_i = 'b0;
        #10 data_i = 8'b0011_0101; set_i = 'b1;
        #40 set_i = 'b0;
        #200 $stop;
    end
endmodule
